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ADM1041
Pin No.
21
22
23
24
Mnemonic
V S +
SCMP
SHRS+
SHRO
Description
This pin is the positive remote load voltage sense input and is normally divided down from the power
supply output voltage to 2.0 V at no load using an external voltage divider. The input impedance is
high.
Output of the Current Share Transconductance Error Amplifier. Compensation is a series capacitor and
resistor to ground. While V DD is normal and PEN is false, this pin is clamped to ground. When the
converter is enabled (PEN true) and the clamp is released, the compensation capacitor charges
providing a slow walk-in. The error amplifier input has a built-in bias so that all slaves in a parallel
supply system do not compete with the master for control of the share bus.
Current Share Sense. This is the noninverting input of a differential sense amplifier looking at the
voltage on the share bus. For testing purposes, this pin is normally connected to SHRO. Calibration
always expects this pin to be at 2.0 V with respect to SHRS–/V S –. If a higher share voltage is required, a
resistor divider from SHRO or an additional gain stage, as shown in the application notes, must be
used.
Current Share Output. This output is capable of driving the share bus of several power supplies
between 0 V and V DD – 0.4 V (10 k? bus pull-down in each supply). Where a higher share bus voltage is
required, an external amplifier is necessary. The current share output from the supply which, when
bused with the share output of other power supplies working in parallel, allows each of the supplies
to contribute essentially equal currents to the load.
Table 4. Default Pin States during EEPROM Download
Pin No.
11
12
17
18
19
Mnemonic
CBD
PEN
DC_OK
AC_OK
F G
State
High impedance (Hi-Z) at power-up and until the end of the EEPROM download (approximately 20 ms).
This pin is reconfigured at the end of the EEPROM download.
High impedance (Hi-Z) at power-up and until the end of the EEPROM download (approximately 20 ms).
This pin is reconfigured at the end of the EEPROM download.
Active low (low if DC_OK true) at power-up.
This pin is reconfigured during the EEPROM download.
Active low (low if DC_OK true) at power-up.
This pin is reconfigured during the EEPROM download.
High impedance (Hi-Z) at power-up and until the end of the EEPROM download (approximately 20 ms).
This pin is reconfigured at the end of the EEPROM download.
Rev. A | Page 16 of 64
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